The present invention relates to a memory tester for testing semiconductor-integrated memories.
FIG. 1 shows the construction of a conventional memory tester, which comprises a pattern generator 1, a programmable data selector 2, for selecting pins of a memory under test 5 to be supplied with test patterns a formatter 3, drivers 4 for,/applying a pattern signal and an address signal to the memory under test 5, a comparator 6 for making comparison between data read out of the memory under test 5 and an expected value derived from the pattern generator 1, and a failure analysis memory 7 which responds to the detection of non-coincidence by the comparator 6 to store a "1" in the same address as that supplied to the memory under test 5 to thereby store a defective address of the memory 5.
Usually, an operator predetermines data patterns and address patterns to be generated by the pattern generator 1 in accordance with the kind of memory to be tested, prepares a program for generating such patterns and sets it in the pattern generator 1. The memory under test 5 is accessed by an address signal A from the pattern generator 1, a data pattern signal D is written into the accessed address, and data D' read out therefrom is compared with an expected value E by the comparator 6. When non-coincidence is detected between the read-out data D' and the expected value E, a "1" indicating a failure is written into the same address of the failure analysis memory 7 as the address from which the data D' was read out.
Some of memories now in use are of the type that are supplied with a clock from the outside and create an address signal, such as a FIFO (First-In First-Out) memory and a SAM (Serial Access Memory) in a dual port memory.
Also in testing such a memory, it is necessary in the prior art to prepare a program for causing the pattern generator 1 to generate the same address signal as that created in the memory under test, and the address signal produced by the pattern generator 1 is provided to the failure analysis memory 7 to store therein failure analysis data.
Another type of memory is one that is commonly referred to as STRAM (Self-Timed RAM), and this provides read-out data several cycles behind the input of an address signal.
This memory has pipeline registers 5B and 5C at both input and output sides of a memory 5A as shown in FIG. 2, for instance. Input data pattern D and address pattern A pass through respective stages of the pipeline register 5A in synchronism with a clock signal CK and are applied to the memory 5A, and data D' read out therefrom is output via respective stages of the pipeline register 5C in synchronism with the clock signal CK. Consequently, the data D' is delayed for cycles of the same number as the sum of the numbers of stages of the pipeline registers 5B and 5C with respect to the input read address A.
Assume that each of the pipeline registers 5B and 5C has two stages. When applying address signals A.sub.1, A.sub.2, A.sub.3, A.sub.4, . . . to the memory under test 5 as depicted in FIG. 3A, its read-out data D.sub.1 ', D.sub.2 ', D.sub.3 ', D.sub.4 ' . . . are each delivered four test cycles (i.e. four clock cycles) behind the corresponding address signal as shown in FIG. 3B.
In this instance, if the result of comparison F.sub.1 shown in FIG. 3C is written into the failure analysis memory 7 four test cycles behind the corresponding address signal, then the failure analysis memory 7 is accessed at an address A.sub.5, wherein the result of comparison F.sub.1 of the data D.sub.1 read out from the address A.sub.1 of the memory under test 5 will be stored. Accordingly, in the test of such a memory it is necessary to make the failure analysis bearing in mind the correct correspondence between addresses of the failure analysis memory and addresses of the memory under test. In practice, however, this is very cumbersome. Further, it is very likely to misunderstand that addresses of the failure analysis memory and the memory under test have a direct one-to-one correspondence.